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High performance asynchronous FIR filter design in GaAs

Montiel-Nelson, J and Nooshabadi, SV (1997). High performance asynchronous FIR filter design in GaAs. Circuits, Devices and Systems,144(5):289-296.

Document type: Journal Article
Citation counts: TR Web of Science Citation Count  Cited 1 times in Thomson Reuters Web of Science Article | Citations
Scopus Citation Count Cited 1 times in Scopus Article | Citations
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ISI LOC 000073870400007
Title High performance asynchronous FIR filter design in GaAs
Author Montiel-Nelson, J
Nooshabadi, SV
Journal Name Circuits, Devices and Systems
Publication Date 1997
Volume Number 144
Issue Number 5
ISSN 1350-2409   (check CDU catalogue open catalogue search in new window)
Scopus ID 2-s2.0-0031244628
Start Page 289
End Page 296
Total Pages 8
Place of Publication uk
Publisher IEEE
HERDC Category C1 - Journal Article (DEST)
Abstract An asynchronous FIR architecture design using a mixed mode logic approach in GaAs technology is presented. Combining an asynchronous design style with static and dynamic logic proves to be very suitable for high speed and low power implementation of real time mobile computing applications. The authors introduce a novel clocked dynamic latched (CDL) logic in GaAs to implement the micropipeline latches required in the single phase signalling. The reliable implementation of an 11-tap FIR filter in terms of speed, area and power dissipation in GaAs MESFET 0.6μm Vitesse technology is demonstrated. This ASIC system is fully operative across the full range of process spread variations and the temperature range of 0 to 100°C. It is robust against power supply variations of 15%.
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