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Micropipeline Architecture for Multiplier-less FIR Filter

Nooshabadi, S, Montiel-Nelson, J, Visweswaran, GS and Nagchoudhurhi, D (1997). Micropipeline Architecture for Multiplier-less FIR Filter. In: 10th International Conference on VLSI Design: VLSI in Multimedia Applications, India, 4-7 January 1997.

Document type: Conference Paper
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Author Nooshabadi, S
Montiel-Nelson, J
Visweswaran, GS
Nagchoudhurhi, D
Title Micropipeline Architecture for Multiplier-less FIR Filter
Conference Name 10th International Conference on VLSI Design: VLSI in Multimedia Applications
Conference Location India
Conference Dates 4-7 January 1997
Place of Publication USA
Publisher IEEE
Publication Year 1997
ISSN 0-8186-775   (check CDU catalogue open catalogue search in new window)
Start Page 451
End Page 456
HERDC Category E1 - Conference Publication (DEST)
Abstract In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropiplined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.
 
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Created: Fri, 12 Sep 2008, 08:35:25 CST by Administrator