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A Novel Latch Design for High-Speed GaAs Circuits

Nooshabadi, SV, Montiel-Nelson, JA and Eshraghian, K (1997). A Novel Latch Design for High-Speed GaAs Circuits. In: 14th Australian Microelectronics Conference, Melbourne, 29 September - 1 October 1997.

Document type: Conference Paper
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Author Nooshabadi, SV
Montiel-Nelson, JA
Eshraghian, K
Title A Novel Latch Design for High-Speed GaAs Circuits
Conference Name 14th Australian Microelectronics Conference
Conference Location Melbourne
Conference Dates 29 September - 1 October 1997
Place of Publication Australia
Publisher IREE
Publication Year 1997
ISBN 0909394 43   (check CDU catalogue open catalogue search in new window)
Start Page 51
End Page 54
HERDC Category E5 - Conference Publication - Refereed without National or International significance (internal)
Abstract A GaAs latch design suitable for dynamic logic families is presented. This novel concept is compared with other common GaAs logic circuits in terms of device count, area, clock rate and power consumption. The results demonstrate that the Single Phase Latch (SPL) achieves a throughput 5.7 greater than other dynamic latches while driving twice the capacitive load. It is the simplest, the fastest and consumes less power than other reported dynamic latch structures
 
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Created: Fri, 12 Sep 2008, 08:35:25 CST by Administrator