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Design of a quasi-cyclic low density parity check code for binary erasure channels

Nheu, Christopher (2017). Design of a quasi-cyclic low density parity check code for binary erasure channels. Bachelor of Engineering Co-op (4th Year Project) Thesis, Charles Darwin University.

Document type: Thesis
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Author Nheu, Christopher
Title Design of a quasi-cyclic low density parity check code for binary erasure channels
Institution Charles Darwin University
Publication Date 2017-05
Thesis Type Bachelor of Engineering Co-op (4th Year Project)
Supervisor Vafi, Sina
0906 - Electrical and Electronic Engineering
Abstract All digitally transmitted message signals suffer from noise. Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes are a family of structured LDPC codes that are capable of high performance error correcting capabilities. The aim of this thesis is to design a QC-LDPC code to correct messages passed through the binary erasure channel (BEC). The BEC is a channel model in which bits received correctly are known, or are unknown if received incorrectly.

All types of LDPC codes are sparse matrices of many 0s and very few 1s. The placement of these 1s determines how well a code can correct errors. In theory, 1s can be placed in any configuration that gives high error correcting performance. However, this will likely come at the cost of complex hardware implementation. To compensate for this trade-off, QC-LDPC codes follow a specific structure in the placement of 1s to make the hardware implementation more efficient.

In this thesis, a literature review of QC-LDPC codes is undertaken, codes are then designed and their performance verified by simulation on MATLAB. It also aims to implement QC-LDPC codes in hardware using the hardware description language VHDL. Testing of the hardware implementation is carried out by hardware simulation using the ModelSim software. The results of the software simulations shows that well designed QC- LDPC codes with girth of at least 6 are close to 0.1 from the Shannon Limit in the BEC. The hardware simulation expresses that decoding erasures from the BEC can occur rapidly in the range of megabits per second, which is significantly quicker than software simulations. It also demonstrates that the implementation of QC-LDPC codes in hardware have linear complexity proportional to the length of the message blocks of the code

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Created: Fri, 23 Jun 2017, 15:57:49 CST by Jessie Ng